library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ledflash is
port (
		mclk:						in	std_logic;
		oaled,dataled:				in	std_logic;
		videoled:			        in	std_logic_vector(15 downto 0);		
		clock_led:					out	std_logic;
		data_led:					out std_logic
	);
end ledflash;		
architecture be of ledflash is

signal cn		:	std_logic_vector(10 downto 0);
signal led_inbuf: 	std_logic_vector(23 downto 0);
--signal led_inbuf: 	std_logic_vector(19 downto 0);

begin
--led_inbuf(23 downto 0) <= los(0)&fal(0)&ra(0) &los(1)&fal(1)&ra(1) &los(2)&fal(2)&ra(2) &los(3)&fal(3)&ra(3)
--						 &los(4)&fal(4)&ra(4) &los(5)&fal(5)&ra(5) &los(6)&fal(6)&ra(6) &los(7)&fal(7)&ra(7);
led_inbuf(23 downto 16) <=oaled&videoled(0)&videoled(1)&videoled(2)&videoled(3)&videoled(4)&videoled(5)&'1';
led_inbuf(15 downto 8) <=videoled(6)&videoled(7)&videoled(8)&videoled(9)&videoled(10)&videoled(11)&videoled(12)&videoled(13);
led_inbuf(7 downto 0)  <=videoled(14)&videoled(15)&dataled&"11111";

	process(mclk)
	begin
		if mclk'event and mclk = '1' then
			cn <= cn + 1;
		--	if conv_integer(cn)< 40 then
			if conv_integer(cn)< 48 then
				--if cn(0)'event and cn(0) = '0' then
				if cn(0) = '0' then
				   data_led <= led_inbuf(conv_integer(cn)/2);
				end if;
				clock_led <=cn(0);	
			else
				clock_led <='1';
			--	data_led <= '1';
			end if;
		end if;
	end process;	
 end be;